This disclosure relates to image processing apparatuses that perform frame rate conversion processing such as double-rate conversion processing by using pixel data, or image data, stored in frame memories. Specifically, this disclosure relates to image processing apparatuses that compress the pixel data, or the image data, before storing in the frame memories.
Image processing apparatuses such as television sets utilizing liquid crystal displays receive a plurality of types of pixel data, e.g., pixel data of each frame, or field, of standard television images, and pixel data of each frame corresponding to each movie frame of film source images. The image processing apparatuses detect the type of the input pixel data and perform conversion processing in accordance with the detected type and generate output pixel data, which is used to display the image.
Recently, image display apparatuses that perform frame rate conversion, such as an apparatus described in Japanese Laid-open Patent JP 2011-19037 (Patent Document 1), which was filed by this applicant, are commercially used. Such apparatuses receive pixel data of each frame with an input frame rate and perform frame rate conversion processing, such as double-rate conversion processing, by inserting interpolated images between successive frames. The frame rate conversion processing is effective to reduce judders in film source images and to improve response of liquid crystal displays to moving images.
Further, in recent years, image display apparatuses that display 10-bit pixel data are widely used to display precise color levels. Image processing apparatuses used in such display apparatuses receive 10 bit pixel data, which may have a total number of bits of 30 bits including 10 bits for each of R (Red), G (Green), and B (Blue) primary colors. Conventionally, image processing apparatuses that perform double-rate conversion operation store the entire bits of the 10-bit input pixel data and 10-bit interpolated pixel data in frame memories.
When displaying moving images, human eyes cannot distinguish between images displayed with 10-bit pixel data and images displayed with 8-bit pixel data. Accordingly, pixel data with 8-bit resolution is sufficient for displaying moving images. When displaying still images, on the other hand, human eyes can clearly distinguish between images displayed with 10-bit pixel data and images displayed with 8-bit pixel data. Accordingly, pixel data with 10-bit resolution is preferably used to display still images.
A technique is proposed to utilize this characteristic of human eyes. That is, as shown in FIG. 7, input 10-bit pixel data is divided into upper 8-bit bit portions and lower bit portions and separately stored in a frame memory. Further, 8-bit interpolated pixel data is generated by only using the upper bit portions of the input pixel data and stored in the frame memory. The 8-bit interpolated pixel data is added with lower 2-bit portions of the input pixel data to generated 10-bit interpolated pixel data, which is used to display the interpolated image.
In the image processing apparatus 50 shown in FIG. 7, a dividing circuit 52 divides 10-bit input pixel data of the current frame into upper 8-bit bit portions and lower 2-bit portions, and separately stores in respective storage areas of a frame memory 56. Interpolated image generation circuit 54 generates upper 8-bit portions of current frame interpolated pixel data from (i) upper 8-bit portions of current frame pixel data input from the dividing circuit 52, and (ii) upper 8-bit portions of previous frame input pixel data read from the frame memory 56. Upper 8-bit portions of current frame interpolated pixel data generated by the interpolated image generation circuit 54 are stored in the frame memory 56.
Then, the adder 58 adds (i) each of upper 8-bit portions of the input pixel data or the interpolated pixel data, which are read from the frame memory 56 in a predetermined order, and (ii) corresponding one of lower 2-bit portions of the input pixel, which are also read from the frame memory 56. Thereby, 10-bit output pixel data is generated.
Japanese Laid-open Patent JP 2008-304763 (Patent Document 2) describes another technique. That is, (i) upper bit portions and lower bit portions of display field data are stored in separate storage areas in a frame memory, and (ii) as the previous frame display data, which is used in moving image emphasis processing unit, only the upper bit portions are read from the frame memory.
However, these prior art image processing apparatuses that perform frame rate conversion operation require storing the entire 10-bit input pixel data in frame memories. Larger memory capacity and wider access bandwidth are required for storing 10-bit pixel data than storing 8-bit pixel data. Accordingly, compression of pixel data is often employed. Specifically, upper bit portions of pixel data can be compressed efficiently. For example, upper 8-bit portions of pixel data may be compressed with a compression ratio of 50% before storing in the frame memory.
On the other hand, it is difficult to compress lower bit portions with a high compression ratio. Accordingly, the lower bit portions are usually stored in the frame memory with no compression. If the upper 8-bit portions are compressed with a compression ratio of 50%, and the lower 2-bit portions are not compressed, the total compression ratio is 40%, which is not high enough.